System Verilog Verification Engineer

UST

Full-time Engineers
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Location
Bengaluru, Karnataka, India
Posted
June 07, 2026

Job Description

Hi,


Role and Responsibilities: Power DV Skill Requirements: Good knowledge on SV/UVM Hands-on on SoC Verification AMBA protocol knowledge Power/PMU verification Good debugger skills

Good to have: All of the above Experience: 3 to 5 years


Please share your resume to [email protected]


Regards,

Jaya