Lead MCU/subsystem/block-level closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation.
Collaborate closely with SoC-level teams to align on clocking and floor planning strategies, leveraging strong understanding of SoC methodologies without direct ownership of SoC-level activities.
Work on the different power domains and implement UPF.
Apply knowledge of clocking methodologies to ensure subsystem clock domain integration aligns with overall SoC clock architecture.
Develop and refine subsystem closure methodologies and automation flows to improve design quality and efficiency.
Mentor and guide physical design engineers within the subsystem teams, promoting best practices and methodology adoption.
Work cross-functionally with RTL designers, STA, power, verification, and backend teams to ensure smooth subsystem integration...