Job Description
Position Overview
The Sr. Memory & Storage Architect will own detailed design of the tiered CXL 3.1–class memory subsystem that underpins the next-generation key-value platform. This role defines memory pool architectures, designs Near-Data Processing logic for in-memory KV-cache operations, and partners with system software engineers to expose these capabilities through extended inference runtimes.
Key Responsibilities
▸ Design CXL 3.1–generation Type-2 and Type-3 tiered memory pool architectures supporting hot KV-cache in high-bandwidth memory and cold KV offloaded to DDR5 via intelligent tiering logic.
▸ Architect Near-Data Processing (NDP) engines co-located with CXL memory for attention score computation, KV compression/decompression, and vector operations to minimize CPU round-trips.
▸ Define memory controller microarchitecture, including arbitration policy, prefetching strategies, ECC, and inline encryptio...