Location
Phoenix, AZ, United States
Posted
July 25, 2026
Job Description
**Job Details:**
**Job Description:**
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.
**Responsibilities will include but not limited to:**
- Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
- Participates in the definition of architecture and microarchitecture features of the block being designed.
- Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to en...
**Job Description:**
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.
**Responsibilities will include but not limited to:**
- Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
- Participates in the definition of architecture and microarchitecture features of the block being designed.
- Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to en...