Senior Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL

Full-time Other-General

Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL

• Are you a Mid to Senior level Senior Verification Engineer looking for you next challenge?
• Have experience with SystemVerilog and UVM, plus scripting in Python, Perl, Bash, or TCL?
• Want to join a very exciting Spain based semiconductor company?

If you can say to this, then please keep reading.

We're partnered with a genuinely exciting Barcelona HQ'd semiconductor organization and they're seeking a number of Mid-to-Senior Verification Engineers to join them on a permanent basis, working 100% onsite in central Barcelona.

Visa sponsorship is available if needed, plus free Spanish lessons to help you assimilate in Spain.

Required skills:

• MSc or PhD in a related field
• 4+ years relevant experience
• Proficiency in SystemVerilog and UVM
• Knowle...