Location
, penang, malaysia, penang, Malaysia
Posted
July 25, 2026
Job Description
Jobtailor in Malaysia is seeking an experienced RTL design verification engineer to develop functional verification plans and test benches covering microarchitectural specs. The role requires collaboration with architects and RTL/physical teams, using SystemVerilog and UVM/OVM for thorough pre-silicon validation.
You will execute verification strategies, debug failing tests, and improve verification infrastructure while documenting plans and leading reviews.
#J-18808-Ljbffr