Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
Intel
Full-time
other-general
Location
Santa Clara, CA, United States
Posted
June 03, 2026
Job Description
**Job Details:**
**Job Description:**
**About the Role**
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.
In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
**What You’ll Do**
**Key responsibilities will include but not limited to:**
+ Developing layout design methodology for testchip development in next generation process nodes
+ Working closely with Process Integration, Yield and QnR to ...
**Job Description:**
**About the Role**
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.
In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
**What You’ll Do**
**Key responsibilities will include but not limited to:**
+ Developing layout design methodology for testchip development in next generation process nodes
+ Working closely with Process Integration, Yield and QnR to ...