Senior Front-End ASIC Engineer: RISC-V Core & IP

Bitdeer

Full-time Other-General
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Location
singapore, singapore, Singapore
Posted
July 22, 2026

Job Description

Bitdeer, headquartered in Singapore, seeks an experienced CPU Core Integration & Verification Engineer to drive the RISC-V core integration with external accelerators and tailor features for strict PPA requirements.

You will modify RTL in Verilog/SystemVerilog, collaborate with performance and back-end teams, and support ASIC FE execution and DV across pre- and post-silicon stages. Bitdeer offers a fast-growing, inclusive environment.

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