Location
bayan lepas, penang, Malaysia
Posted
June 01, 2026
Job Description
A leading global semiconductor company located in Penang, Malaysia, is seeking an experienced engineer to collaborate with IP designers on FPGA timing models. The ideal candidate will have over 10 years of hardware integration design experience, proficiency in Cadence Virtuoso, and knowledge of static timing analysis. This role offers the opportunity to work in a fast-paced environment alongside a dedicated team. Competitive compensation and development opportunities are provided.
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