Location
San Jose, California, United States
Posted
July 02, 2026
Job Description
Job DescriptionWe are looking for an experienced senior design verification architect to lead verification strategy, methodology, and architecture for HPC SOCs, subsystems, and IP blocks. You will define end-to-end DV plans, guide teams to methodology and coverage goals, and ensure high-quality silicon through robust verification infrastructure.
1. Verification strategy and architecture: Define and document the global verification strategy, testbench architecture, and methodologies.
2. Methdology leadership: Drive the adoption of industry-standard methodologies and best practices to maximuze verification efficiency and reuse.
3. AI workload verification: Develop strategies to verify complex dataflow architectures using real world AI workloads.
4. Cross-functional collaboration: Work closely with RTL designers, system architects, and firmware engineers to identify edge cases and resolve complex hardware bugs.
#LI-YS1Requirement1. Master's degree in Electica...
1. Verification strategy and architecture: Define and document the global verification strategy, testbench architecture, and methodologies.
2. Methdology leadership: Drive the adoption of industry-standard methodologies and best practices to maximuze verification efficiency and reuse.
3. AI workload verification: Develop strategies to verify complex dataflow architectures using real world AI workloads.
4. Cross-functional collaboration: Work closely with RTL designers, system architects, and firmware engineers to identify edge cases and resolve complex hardware bugs.
#LI-YS1Requirement1. Master's degree in Electica...