Location
ottawa, on, Canada
Posted
July 16, 2026
Job Description
Join Synopsys as a Senior ASIC Digital Design Engineer and leverage your expertise in high-speed digital and mixed-signal interfaces. Collaborate with global teams to create ground-breaking RTL designs in a hybrid work environment.
At Synopsys, we seek passionate engineers with 7-10 years of experience in ASIC design. Your deep knowledge of RTL design and physical implementation will drive innovative HBM PHY IP solutions. You will mentor junior engineers and contribute to cutting-edge developments while communicating complex technical concepts effectively.
Key Responsibilities:
• Develop RTL designs for High Bandwidth Memory PHY IP
• Translate architectural specifications into high-performance RTL
• Collaborate with cross-functional teams for optimal design integration
• Innovate solutions for timing closure and low power design
• Automate design and verification tasks for increased efficiency
Requirements:
• 7-...
At Synopsys, we seek passionate engineers with 7-10 years of experience in ASIC design. Your deep knowledge of RTL design and physical implementation will drive innovative HBM PHY IP solutions. You will mentor junior engineers and contribute to cutting-edge developments while communicating complex technical concepts effectively.
Key Responsibilities:
• Develop RTL designs for High Bandwidth Memory PHY IP
• Translate architectural specifications into high-performance RTL
• Collaborate with cross-functional teams for optimal design integration
• Innovate solutions for timing closure and low power design
• Automate design and verification tasks for increased efficiency
Requirements:
• 7-...