Senior Analog Layout Engineer

Full-time Engineering

We are seeking a highly skilled Senior Layout Engineer to lead the physical implementation of critical analog and mixed-signal blocks. You will work closely with circuit designer to translate schematics into high performance, DRC/LVS-clean layouts for advanced process Nodes (e.g., 40nm, 22nm). This role demands deep knowledge of parasitic effects, matching, and isolation techniques.

Key Responsibilities

• Execute full custom analog layout for blocks such as ADCs/DACs, PLLs, BG, LDOs, OPAMP, and SerDes.
• Optimize layout for matching, minimal parasitic capacitors and resistors, and power/gnd distribution.
• Perform parasitic extraction, EM/IR analysis, and Reliability checks.
• Drive layout vs. schematic (LVS) and design rule check (DRC) closure.
• Collaborate with circuit designers to propose floorplans and resolve trade-offs.

Required Qualifications:

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