Location
San Jose, California, United States
Posted
July 21, 2026
Job Description
Job DescriptionWe are seeking a high-caliber Engineer to lead the architectural design and development of a next-generation Top-level Integration Flow.
Your mission is to build a highly automated framework—comparable to SoC Compiler—that streamlines the path from IP handoff to full-chip netlist generation.
Key Responsibilities:
• Framework Architecture: Design and implement a scalable SoC assembly framework using Python, Perl, Tcl or C++ to automate connectivity, memory map generation, and clock/reset structures.
• Metadata Standardization: Define and leverage metadata standards (e.g., IP-XACT) to enable seamless IP integration and configuration.
• Tool Development: Build advanced SoC Compiler capabilities, including automated RTL generation, stitch-rule checking (LINT/CDC), and synthesis-ready top-level packaging.
• Optimization: Collaborate with Front-End and Physical Design teams to integrate PPA-driven constraints into the automation pipeline.
Your mission is to build a highly automated framework—comparable to SoC Compiler—that streamlines the path from IP handoff to full-chip netlist generation.
Key Responsibilities:
• Framework Architecture: Design and implement a scalable SoC assembly framework using Python, Perl, Tcl or C++ to automate connectivity, memory map generation, and clock/reset structures.
• Metadata Standardization: Define and leverage metadata standards (e.g., IP-XACT) to enable seamless IP integration and configuration.
• Tool Development: Build advanced SoC Compiler capabilities, including automated RTL generation, stitch-rule checking (LINT/CDC), and synthesis-ready top-level packaging.
• Optimization: Collaborate with Front-End and Physical Design teams to integrate PPA-driven constraints into the automation pipeline.