Principal engineer – chip design front end ( fortune500 organization )
Mulya Technologies
Full-time
Engineers
Location
Bengaluru, Karnataka, India
Posted
June 06, 2026
Job Description
Fortune 500 Organization
Bengaluru, Karnataka, India ·
Principal Engineer – Chip Design Front End
We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in So C design, RTL coding, verification planning, and project management.
This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.
* Target products are not FPGA-based.*
* Experience with MCU products featuring ARM cores is preferred. *
Key Skills - Priority Level (1(Low) - 5(High))
Chip Level Verification – 5
Chip-Level Use Case Understa...
Bengaluru, Karnataka, India ·
Principal Engineer – Chip Design Front End
We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in So C design, RTL coding, verification planning, and project management.
This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.
* Target products are not FPGA-based.*
* Experience with MCU products featuring ARM cores is preferred. *
Key Skills - Priority Level (1(Low) - 5(High))
Chip Level Verification – 5
Chip-Level Use Case Understa...