Location
Bangalore, India, India
Posted
June 27, 2026
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companiesDeep expertise in SystemVerilog and UVM (Universal Verification Methodology)Strong understanding of digital design fundamentals — RTL, timing, clocking, resetsExperience with industry-standard simulators: Xcelium, VCS, QuestaProficiency in coverage-driven verification — functional, code, and toggle coverageHands-on experience with formal verification tools and flowsExperience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similarStrong debug skills — waveform analysis (Verisium, SimVision)Familiarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation
Core Responsibilities
Strategy and ArchitectureVerification Planning: Define the overall verification strategy, including the choice of ...
B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companiesDeep expertise in SystemVerilog and UVM (Universal Verification Methodology)Strong understanding of digital design fundamentals — RTL, timing, clocking, resetsExperience with industry-standard simulators: Xcelium, VCS, QuestaProficiency in coverage-driven verification — functional, code, and toggle coverageHands-on experience with formal verification tools and flowsExperience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similarStrong debug skills — waveform analysis (Verisium, SimVision)Familiarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation
Core Responsibilities
Strategy and ArchitectureVerification Planning: Define the overall verification strategy, including the choice of ...