Location
Goleta, CA, United States
Posted
July 21, 2026
Job Description
Job Description
Job Overview
We are seeking a Physical Design Engineer to support the implementation of complex ASIC/SoC designs from synthesis through tapeout. This role is responsible for physical design execution, timing closure, physical verification, DFT integration, and design optimization while collaborating with cross-functional engineering teams to deliver high-quality, manufacturable silicon.
Key Responsibilities
• Perform full-chip and block-level physical design including synthesis, DFT integration, floorplanning, power planning, placement, CTS, routing, post-route optimization, and timing closure.
• Drive timing closure across all corners and modes, addressing setup/hold, signal integrity, and IR/EM requirements.
• Develop and improve physical design and DFT methodologies, flows, and automation.
• Analyze and resolve timing, congestion, power, and implementation issues.
• Perform physical verification including DRC, LVS, and antenna check...
Job Overview
We are seeking a Physical Design Engineer to support the implementation of complex ASIC/SoC designs from synthesis through tapeout. This role is responsible for physical design execution, timing closure, physical verification, DFT integration, and design optimization while collaborating with cross-functional engineering teams to deliver high-quality, manufacturable silicon.
Key Responsibilities
• Perform full-chip and block-level physical design including synthesis, DFT integration, floorplanning, power planning, placement, CTS, routing, post-route optimization, and timing closure.
• Drive timing closure across all corners and modes, addressing setup/hold, signal integrity, and IR/EM requirements.
• Develop and improve physical design and DFT methodologies, flows, and automation.
• Analyze and resolve timing, congestion, power, and implementation issues.
• Perform physical verification including DRC, LVS, and antenna check...