Job Description
Job Description:
Architecture & Design
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Define FPGA architecture for protocol filtering, deep packet inspection, and capture engines.
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Design RTL for hardware accelerators, high-speed bus interfaces, and external memory controllers.
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Implement demodulators and decoders for Bluetooth (LE, Classic) and proprietary protocols.
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Optimize FPGA resources to maximize timing closure, throughput, and clock frequencies.
Leadership & Collaboration
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Lead engineers through the complete FPGA development lifecycle from concept to hardware timing closure.
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Collaborate closely with RF boards, software drivers, and system validation teams.
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Mentor junior and mid-level digital design and FPGA implementation engineers.
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Drive code reviews to maintain high-quality RTL and synthesis standards.
Verif...