Logic Design & Verification Engineer (RTL / UVM / ASIC Development)

Full-time Other-General

My Client:

My client is a fast-growing global technology company building high-performance chip systems for large-scale computing applications. The engineering team focuses on digital front-end design and verification, delivering robust and scalable ASIC solutions.The team works in a highly collaborative and engineering-driven environment, combining RTL design, verification methodologies, and system-level optimization. They are currently expanding their front-end engineering team to support next-generation chip development.

Job Responsibilities:

• Design and implement RTL modules using Verilog/SystemVerilog for ASIC/SoC projects.
• Develop and execute verification plans, including testbench development using UVM methodology.
• Perform functional verification, debugging, and coverage analysis to ensure design correctness.
• Participate in SoC integration, testability (DFT) design, and overall front-end devel...