Lead Physical Design Engineer - Low-Power ASICs

Cadence

Full-time Design & Development
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Location
Remote, Remote, Finland
Posted
July 18, 2026

Job Description

Cadence Finland is seeking an experienced Application Engineer focused on physical design for ASIC and heterogeneous designs, aiming for low power and high-speed solutions at advanced nodes. You will lead full design flows and collaborate with RTL teams to enable successful tapeouts.

The role requires hands-on expertise across floorplanning, place-and-route, clock tree synthesis, timing closure, and sign-offs, with a strong emphasis on EM/IR analysis and DFM.

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