Location
singapore, singapore, Singapore
Posted
July 07, 2026
Job Description
F10N/W CMOS Matching and RegE Wafer Edge Exclusion (WEE) Program
The intern will be responsible for driving yield improvement initiatives through CMOS matching analysis and RegE Wafer Edge Exclusion (WEE) program. The role focuses on identifying inline mismatches, reducing wafer edge‑related yield loss, and developing robust analytical solutions to enable sustainable manufacturing performance.
Key Responsibilities- Conduct fab‑to‑fab offload interaction studies to identify and diagnose inline mismatches between N and W processes that contribute to yield differences.
- Perform detailed bevel characterization to assess defectivity performance differences and quantify their impact on inline die loss.
- Analyze cross‑module data to establish root‑cause relationships between process variation and yield performance.
- Drive key WEE performance metrics, including 22UE capability and 1H edge coat performance, to maximize overall yield.
- ...