Intern: Application Engineering - Silicon Signoff and Verification

Cadence Design Systems, Inc.

Part time Engineers
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Location
Belo Horizonte, State of Minas Gerais, Brazil
Posted
June 28, 2026

Job Description

Description

:
  • The Candidate will be trained on the Cadence tool set, in the context of multiple flows for Integrated Circuit (IC) Physical/Signoff, Parasitic Extraction, full-chip electromigration, IR drop and power analysis to support our leading-edge customers meet/exceed their signoff targets, achieve faster design closure, and turn their design concepts into reality. Using Cadence’s suite of tools, you will help develop creative and innovative solutions for customers, benchmark product capabilities for a wide range of flow regimes and phenomena, advocate for best practices, and collaborate with members of the sales and product teams.

    • Key responsibilities in this position are to:

  • Helping customers to adopt and proliferate our IC Signoff solutions
  • Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations
  • Supporting technical evaluations and benchmar...

    • Job Details

    • Job Type
      Part time
    • Category
      Engineers
    • Date Posted
      June 28, 2026
    • Application Deadline
      August 07, 2026