Hybrid Senior RTL Design Engineer – SoC & PD Lead
Cisco Systems, Inc.
Full-time
Construcción, diseño y desarrollo
Location
capital, quindío, Colombia
Posted
July 19, 2026
Job Description
Cisco Silicon One Team in Armenia is hiring a senior ASIC digital design engineer. The role involves contributing to RTL design, sub-system integration, and improving design flows. You will collaborate with verification and physical design teams to deliver high-quality silicon.
Requires 6+ years in ASIC design, strong Verilog/SystemVerilog skills, and scripting in Python/Tcl/Make. Hybrid work setup includes four days at Cisco’s Yerevan office and cross-team collaboration.
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