Front End ASIC RTL/Logic Verification Engineer

Altera

Full-time Engineering
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Location
bayan lepas, penang, Malaysia
Posted
June 02, 2026

Job Description

Responsibilities

  • Develops the verification plan to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
  • Supports SoC customers to ensure high-quality integration and verification of the IP block.
  • Drives quality assurance compliance for smooth IP-SoC handoff.

Qualifications

  • BS/MS or PhD in Electronics Engineering
  • Strong communication, leadership, investigation, problem solving & analytical skill
  • Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
  • Knowledge of scripting is an advantage

Job Details

Job Type: Regular

Shift: Shift 1 (Malaysia)

Primary Location: Penang 15, Penang, Malaysia

Posting Statement

All qualified applicants will receive consideration for employment withou...