Location
, penang, malaysia, penang, Malaysia
Posted
July 27, 2026
Job Description
Altera invites a SOC Timing Engineer in Penang to own timing closure for FPGA/SoC and subsystems. You will perform static timing analysis, derive interface timing constraints, and drive final timing signoff. You will collaborate with design, architecture and physical design teams to converge timing and meet 10nm or lower tapeout readiness.
Candidates should have strong communication and analytical skills. Regular full-time role based in Penang with a shift 1 Malaysia.
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