Location
Fremont, California, United States
Posted
July 08, 2026
Job Description
Qualifications:
Responsibilities:
- Bachelor’s degree in electrical engineering.
- 5 + years of large high speed FPGA design relevant experience.
- Verilog
- Wafer-level semiconductor testing
- Design Experience using the internal PLL circuits (phase lock loops)
- Experience with design of Embedded Algorithmic Pattern Generator (APG) core & the interface between the APGs and the Pin Electronics I/O
- Good understanding of timing constraints in the FPGA to be able to achieve consistent timing results from build to build
Responsibilities:
- Design the timing generators. The timing generators require fine timing control inside the FPGA.
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