Design Verification engineer/Senior (System Verilog/UVM)

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Full-time Engineers
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Location
Ho Chi Minh City, Hα»“ ChΓ­ Minh, Vietnam
Posted
July 26, 2026

Job Description

Job Description:

Job Ref: QV79VR4R

Title: Design Verification Engineer


Location: Onsite in HCM City


Requirements:

4+ years experience with Design Verification


Strong experience with SystemVerilog


Strong experience developing test benches with UVM


Strong experience implementing test cases with UVM


Experience with standard interfaces such as I2C, UART, SPI, AMBA, AHB, USB, etc.


Experience with these interfaces is a bonus: PCIe, UCIe, CXL, Ethernet

Contact: Phuong Le - 0903432692 - [email protected]Β 

Required Skills:

Design