Location
singapore, singapore, Singapore
Posted
June 13, 2026
Job Description
Design Verification Engineer Experience : 4+ Years Salary Range :SGD
Skills Required: FPGA SoC Verification Skills ASIC SoC Verification Skills System Verilog and UVM Skills Automation Skills . IP Verification Skills Low power UPF based verification skills
Technical Expertise Languages :Verilog, System Verilog, C, C++. Verification Methodologies:UVM, OVM. Scripting Languages:Perl,C-shell. Simulators:Cadence IUS, Synopsys VCS, Verdi. Protocols:PCIe,AGPT,CFDM,SPI,ISO7816, DDR3, LPDDR2, GPIO, AXI, AHB, APB, JTAG, WDT, GPT.
Skills Required: FPGA SoC Verification Skills ASIC SoC Verification Skills System Verilog and UVM Skills Automation Skills . IP Verification Skills Low power UPF based verification skills
Technical Expertise Languages :Verilog, System Verilog, C, C++. Verification Methodologies:UVM, OVM. Scripting Languages:Perl,C-shell. Simulators:Cadence IUS, Synopsys VCS, Verdi. Protocols:PCIe,AGPT,CFDM,SPI,ISO7816, DDR3, LPDDR2, GPIO, AXI, AHB, APB, JTAG, WDT, GPT.