Design Verification (DV) Engineer

Lattice Semiconductor

Full-time Engineering
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Location
bayan lepas, penang, Malaysia
Posted
June 05, 2026

Job Description

Overview

Lattice is an international, service-driven developer of programmable design solutions. Our focus is on R&D, product innovation, and customer service to deliver low cost, low power programmable devices. This section provides context for the role.

Responsibilities

  • Develop and review test plans based on design specifications
  • Develop constrained-random verification environments for complex DUTs
  • Implement coverage metrics using cover points and assertions
  • Create and debug tests for DUT
  • Resolve bugs with remote designers

Qualifications

  • Good understanding of verification process from test plan to coverage completion
  • Strong communication and analytical skills
  • Understanding of HDL (Verilog, SystemVerilog)
  • Experience with designing with FPGA is a plus
  • Programming skills (e.g.: C/C++, Perl, TCL or Python)
  • Experience in the foll...