Location
Sunnyvale, CA, United States
Posted
July 13, 2026
Job Description
ASIC Design Verification Technical Lead, TPU
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Advanced**
Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 10 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
+ Experience developing and maintaining verification testbenches, test cases, and test environments.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
+ Experience with universal verification methodology (UVM), SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc.
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Advanced**
Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 10 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
+ Experience developing and maintaining verification testbenches, test cases, and test environments.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
+ Experience with universal verification methodology (UVM), SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc.