ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration
Amazon
Full-time
other-general
Location
Austin, TX, United States
Posted
July 04, 2026
Job Description
Description
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.
Key job responsibilities
As an ASIC Design Engineer, you will:
• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, ...
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.
Key job responsibilities
As an ASIC Design Engineer, you will:
• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, ...