Location
singapore, singapore, Singapore
Posted
July 08, 2026
Job Description
Responsibilities
- Design high-speed (>100MS/s) Successive Approximation Register (SAR) ADCs for applications like 5G, radar, and data converters.
- Optimize critical blocks: capacitor DAC arrays, high-speed comparators, bootstrapped switches, and digital control logic.
- Achieve target specifications: ENOB (Effective Number of Bits), SFDR (Spurious-Free Dynamic Range), power efficiency (FOM < 10 fJ/step).
- Mitigate nonlinearity via capacitor matching techniques (common-centroid, dummy units).
- Reduce kickback noise, clock jitter, and metastability in comparators.
- Develop calibration algorithms (e.g., background LMS for capacitor mismatch).
- Model parasitics, device mismatch, and PVT (Process-Voltage-Temperature) variations.
- Collaborate with layout teams on matched routing, shielding, and EM/IR reliability. ...